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SOC CFGS 参考

SOC CFG

enum wm_rcc_type_t

Values:

enumerator WM_RCC_TYPE_PERIPHERAL

enumerator WM_RCC_TYPE_WLAN

enumerator WM_RCC_TYPE_CPU

enumerator WM_RCC_TYPE_SD_ADC

enumerator WM_RCC_TYPE_QFLASH

enumerator WM_RCC_TYPE_GPSEC

enumerator WM_RCC_TYPE_RSA

enumerator WM_RCC_TYPE_APB

enumerator WM_RCC_TYPE_MAX

enum wm_pmu_clock_source_t

Values:

enumerator WM_PMU_CLOCK_SRC_32K: Using internal 32K crystal oscillator

enumerator WM_PMU_CLOCK_SRC_40M_DIV: Using external 40M crystal oscillator by frequency division

enum wm_timer_id_t

Values:

enumerator WM_TIMER_ID_0

enumerator WM_TIMER_ID_1

enumerator WM_TIMER_ID_2

enumerator WM_TIMER_ID_3

enumerator WM_TIMER_ID_4

enumerator WM_TIMER_ID_5

enumerator WM_TIMER_ID_MAX

enum wm_dma_ch_e

W800 DMA channel enum.

Values:

enumerator WM_DMA_CH_0

enumerator WM_DMA_CH_1

enumerator WM_DMA_CH_2

enumerator WM_DMA_CH_3

enumerator WM_DMA_CH_4

enumerator WM_DMA_CH_5

enumerator WM_DMA_CH_6

enumerator WM_DMA_CH_7

enumerator WM_DMA_CH_MAX

enum wm_dma_ch_irq_e

dma ch interrupt id

Values:

enumerator WM_DMA_CH_IRQ_0

enumerator WM_DMA_CH_IRQ_1

enumerator WM_DMA_CH_IRQ_2

enumerator WM_DMA_CH_IRQ_3

enumerator WM_DMA_CH_IRQ_4_7

enumerator WM_DMA_CH_IRQ_MAX

enum wm_dma_ch_uart_sel_e

dma uart dma channel

Values:

enumerator WM_DMA_CH_UART0_SEL

enumerator WM_DMA_CH_UART1_SEL

enumerator WM_DMA_CH_UART2_7816_SEL

enumerator WM_DMA_CH_UART3_SEL

enumerator WM_DMA_CH_UART4_SEL

enumerator WM_DMA_CH_UART5_SEL

enumerator WM_DMA_CH_UART_SEL_MAX

enum wm_dma_req_sel_e

dma request source

Values:

enumerator WM_DMA_UART_RX_REQ

enumerator WM_DMA_UART_TX_REQ

enumerator WM_DMA_PWM_CAP0_REQ

enumerator WM_DMA_PWM_CAP1_REQ

enumerator WM_DMA_LSPI_RX_REQ

enumerator WM_DMA_LSPI_TX_REQ

enumerator WM_DMA_ADC_CH0_REQ

enumerator WM_DMA_ADC_CH1_REQ

enumerator WM_DMA_ADC_CH2_REQ

enumerator WM_DMA_ADC_CH3_REQ

enumerator WM_DMA_I2S_RX_REQ

enumerator WM_DMA_I2S_TX_REQ

enumerator WM_DMA_SDIOH_REQ

enumerator WM_DMA_REQ_MAX

enum wm_dma_int_type_e

dma ch interrupt type

Values:

enumerator WM_DMA_INT_BURST_DONE

enumerator WM_DMA_INT_XFER_DONE

enumerator WM_DMA_INT_MAX

enum wm_dma_op_mode_e

dma mode

Values:

enumerator WM_DMA_SW_MODE

enumerator WM_DMA_HW_MODE

enumerator WM_DMA_MODE_MAX

enum wm_dma_chain_mode_e

dma chain mode

Values:

enumerator WM_DMA_CHAIN_MODE_NORMAL

enumerator WM_DMA_CHAIN_MODE_LIST

enumerator WM_DMA_CHAIN_MODE_MAX

enum wm_dma_reload_e

dma auto reload control

Values:

enumerator WM_DMA_RELOAD_DISABLE

enumerator WM_DMA_RELOAD_ENABLE

enumerator WM_DMA_RELOAD_MAX

enum wm_dma_ch_en_ctrl_e

dma ch interrupt control

Values:

enumerator WM_DMA_CH_EN_CTRL_DISABLE

enumerator WM_DMA_CH_EN_CTRL_ENABLE

enumerator WM_DMA_CH_EN_CTRL_MAX

enum wm_dma_warp_mode_ctrl_e

dma warp mode control

Values:

enumerator WM_DMA_WARP_CTRL_DISABLE

enumerator WM_DMA_WARP_CTRL_ENABLE

enumerator WM_DMA_WARP_CTRL_MAX

enum wm_dma_chain_mode_ctrl_e

dma chain mode control

Values:

enumerator WM_DMA_CHAIN_MODE_DISABLE

enumerator WM_DMA_CHAIN_MODE_ENABLE

enumerator WM_DMA_CHAIN_MODE_CTRL_MAX

enum wm_dma_addr_mode_e

dma addr inc mode

Values:

enumerator WM_DMA_ADDR_FIXED

enumerator WM_DMA_ADDR_INC

enumerator WM_DMA_ADDR_RSVD

enumerator WM_DMA_ADDR_WARP

enumerator WM_DMA_ADDR_MAX

enum wm_dma_xfer_uint_e

dma data xfer uint

Values:

enumerator WM_DMA_XFER_UNIT_BYTE

enumerator WM_DMA_XFER_UNIT_HALF_WORD

enumerator WM_DMA_XFER_UNIT_WORD

enumerator WM_DMA_XFER_UINT_MAX

enum wm_dma_burst_uint_e

dma data burst uint

Values:

enumerator WM_DMA_BURST_1UNIT

enumerator WM_DMA_BURST_4UNIT

enumerator WM_DMA_BURST_UNIT_MAX

enum wm_dma_ch_control_e

dma start/stop

Values:

enumerator WM_DMA_START_EN

enumerator WM_DMA_STOP_EN

enumerator WM_DMA_CNTL_EN_MAX

enum wm_dma_running_sts_e

dma running status

Values:

enumerator WM_DMA_IDLE

enumerator WM_DMA_RUNNIG

enumerator WM_DMA_STS_MAX

enum wm_sdh_bus_width_t

sd/sdio host bus width

Values:

enumerator WM_SDH_BUS_WIDTH_1BIT

enumerator WM_SDH_BUS_WIDTH_4BITS

enumerator WM_SDH_BUS_WIDTH_MAX

enum wm_i2c_port_t

i2c device port

Values:

enumerator WM_I2C_PORT_0

enumerator WM_I2C_PORT_NUM

enum wm_i2c_speed_t

i2c transfer speed mode

Values:

enumerator WM_I2C_SPEED_STANDARD: 100KHz

enumerator WM_I2C_SPEED_FAST: 400KHz

enumerator WM_I2C_SPEED_MAX: 400KHz

enum wm_uart_port_t

uart port

;

Values:

enumerator WM_UART_PORT_0

enumerator WM_UART_PORT_1

enumerator WM_UART_PORT_2

enumerator WM_UART_PORT_3

enumerator WM_UART_PORT_4

enumerator WM_UART_PORT_5

enumerator WM_UART_PORT_NUM

enum wm_uart_baudrate_t

uart baudrate, Only these enumeration values are supported

Values:

enumerator WM_UART_BAUDRATE_B600

enumerator WM_UART_BAUDRATE_B1200

enumerator WM_UART_BAUDRATE_B1800

enumerator WM_UART_BAUDRATE_B2400

enumerator WM_UART_BAUDRATE_B4800

enumerator WM_UART_BAUDRATE_B9600

enumerator WM_UART_BAUDRATE_B19200

enumerator WM_UART_BAUDRATE_B38400

enumerator WM_UART_BAUDRATE_B57600

enumerator WM_UART_BAUDRATE_B115200

enumerator WM_UART_BAUDRATE_B230400

enumerator WM_UART_BAUDRATE_B460800

enumerator WM_UART_BAUDRATE_B921600

enumerator WM_UART_BAUDRATE_B1000000

enumerator WM_UART_BAUDRATE_B1250000

enumerator WM_UART_BAUDRATE_B1500000

enumerator WM_UART_BAUDRATE_B2000000

enum wm_uart_data_bits_t

uart data bits

Values:

enumerator WM_UART_DATA_BIT_8

enumerator WM_UART_DATA_BIT_MAX

enum wm_uart_stop_bits_t

uart stop bits

Values:

enumerator WM_UART_STOP_BIT_1

enumerator WM_UART_STOP_BIT_2

enumerator WM_UART_STOP_BIT_MAX

enum wm_uart_parity_t

uart parity check

Values:

enumerator WM_UART_PARITY_NONE

enumerator WM_UART_PARITY_EVEN

enumerator WM_UART_PARITY_ODD

enumerator WM_UART_PARITY_MAX

enum wm_uart_flowctrl_t

uart flow control type

Values:

enumerator WM_UART_FLOW_CTRL_DISABLE

enumerator WM_UART_FLOW_CTRL_RTS

enumerator WM_UART_FLOW_CTRL_CTS

enumerator WM_UART_FLOW_CTRL_RTS_CTS

enumerator WM_UART_FLOW_CTRL_MAX

enum wm_7816_protocol_t

7816 protocol

Values:

enumerator WM_7816_T0

enumerator WM_7816_T1

enum wm_7816_bits_order_t

7816 transfer bits order

Values:

enumerator WM_7816_BITS_LSB

enumerator WM_7816_BITS_MSB

enum wm_7816_stop_bits_t

7816 stop bits

Values:

enumerator WM_7816_STOP_BITS_HALF

enumerator WM_7816_STOP_BITS_ONE_AND_HALF

enumerator WM_7816_STOP_BITS_MAX

enum wm_gpio_dir_t

Values:

enumerator WM_GPIO_DIR_INPUT

enumerator WM_GPIO_DIR_OUTPUT

enum wm_gpio_pupd_t

Values:

enumerator WM_GPIO_FLOAT

enumerator WM_GPIO_PULL_UP

enumerator WM_GPIO_PULL_DOWN

enum wm_gpio_intr_mode_t

Values:

enumerator WM_GPIO_IRQ_TRIG_FALLING_EDGE

enumerator WM_GPIO_IRQ_TRIG_RISING_EDGE

enumerator WM_GPIO_IRQ_TRIG_DOUBLE_EDGE

enumerator WM_GPIO_IRQ_TRIG_LOW_LEVEL

enumerator WM_GPIO_IRQ_TRIG_HIGH_LEVEL

enum wm_gpio_pin_mux_t

Values:

enumerator WM_GPIO_IOMUX_FUN1

enumerator WM_GPIO_IOMUX_FUN2

enumerator WM_GPIO_IOMUX_FUN3

enumerator WM_GPIO_IOMUX_FUN4

enumerator WM_GPIO_IOMUX_FUN5

enumerator WM_GPIO_IOMUX_FUN6

enumerator WM_GPIO_IOMUX_FUN7

enum wm_pwm_channels

PWM channel support.

Values:

enumerator WM_PWM_CHANNEL_0

enumerator WM_PWM_CHANNEL_1

enumerator WM_PWM_CHANNEL_2

enumerator WM_PWM_CHANNEL_3

enumerator WM_PWM_CHANNEL_4

enumerator WM_PWM_CHANNEL_MAX

enum wm_pwm_mode

PWM work mode supported by W800.

Values:

enumerator WM_PWM_OUT_INDPT: independent output mode

enumerator WM_PWM_OUT_2SYNC: two channel sync output mode

enumerator WM_PWM_OUT_ALLSYNC: all channel sync output mode

enumerator WM_PWM_OUT_MC: complement output mode

enumerator WM_PWM_OUT_BRAKE: brake output mode

enumerator WM_PWM_IN_CAP: capture for input mode

enumerator WM_PWM_MODE_MAX

enum wm_pwm_cnt_type

PWM counter type supported by W800.

Values:

enumerator WM_PWM_CNT_TYPE_INC: Edge-aligned mode counter counting mode is increment, for capture mode

enumerator WM_PWM_CNT_TYPE_DEC: Edge-aligned mode counter counting mode is decrement, for PWM mode)

enumerator WM_PWM_CNT_TYPE_CENTER: center-aligned mode, for PWM mode

enumerator WM_PWM_CNT_TYPE_MAX

enum wm_pwm_out_state

PIN state setting for which support capture mode This configure item will be set matched with the output/capture mode.

Values:

enumerator WM_PWM_OUT_EN_STATE_OUT: output state for this PWM IO

enumerator WM_PWM_OUT_EN_STATE_TRI: tristate state for this PWM IO

enum wm_pwm_cap_int_type

PWM interrupt type for capture mode supported by W800.

Values:

enumerator WM_PWM_CAP_INT_RISING: Use rising interrupt

enumerator WM_PWM_CAP_INT_FALLING: Use falling edge interrupt

enumerator WM_PWM_CAP_INT_RIGSING_FALLING: Use both rising and falling edge interrupt

enumerator WM_PWM_CAP_INT_DMA: Use DMA Request Interrupt

enum wm_seg_lcd_duty_sel_t

Values:

enumerator WM_SEG_LCD_DUTY_SEL_STATIC: Static duty

enumerator WM_SEG_LCD_DUTY_SEL_1_2: 1/2 duty cycle

enumerator WM_SEG_LCD_DUTY_SEL_1_3: 1/3 duty cycle

enumerator WM_SEG_LCD_DUTY_SEL_1_4: 1/4 duty cycle

enumerator WM_SEG_LCD_DUTY_SEL_1_5: 1/5 duty cycle

enumerator WM_SEG_LCD_DUTY_SEL_1_6: 1/6 duty cycle

enumerator WM_SEG_LCD_DUTY_SEL_1_7: 1/7 duty cycle

enumerator WM_SEG_LCD_DUTY_SEL_1_8: 1/8 duty cycle

enumerator WM_SEG_LCD_DUTY_SEL_MAX

enum wm_seg_lcd_vlcd_cc_t

Values:

enumerator WM_SEG_LCD_VLCD_CC_2_7V: 2.7V output supply voltage

enumerator WM_SEG_LCD_VLCD_CC_2_9V: 2.9V output supply voltage

enumerator WM_SEG_LCD_VLCD_CC_3_1V: 3.1V output supply voltage

enumerator WM_SEG_LCD_VLCD_CC_3_3V: 3.3V output supply voltage

enumerator WM_SEG_LCD_VLCD_CC_MAX

enum wm_seg_lcd_bias_t

Values:

enumerator WM_SEG_LCD_BIAS_1_4: 1/4 internal bias

enumerator WM_SEG_LCD_BIAS_1_2: 1/2 internal bias

enumerator WM_SEG_LCD_BIAS_1_3: 1/3 internal bias

enumerator WM_SEG_LCD_BIAS_STATIC: Static bias

enumerator WM_SEG_LCD_BIAS_MAX

enum wm_seg_lcd_com_id_t

Values:

enumerator WM_SEG_LCD_COM0: COM0 line

enumerator WM_SEG_LCD_COM1: COM1 line

enumerator WM_SEG_LCD_COM2: COM2 line

enumerator WM_SEG_LCD_COM3: COM3 line

enumerator WM_SEG_LCD_COM4: COM4 line

enumerator WM_SEG_LCD_COM5: COM5 line

enumerator WM_SEG_LCD_COM6: COM6 line

enumerator WM_SEG_LCD_COM7: COM7 line

enumerator WM_SEG_LCD_COM_MAX

enum wm_seg_lcd_hd_t

Values:

enumerator WM_SEG_LCD_DRIVE_STRENGTH_LOW: Low output drive strength

enumerator WM_SEG_LCD_DRIVE_STRENGTH_HIGH: High output drive strength

enumerator WM_SEG_LCD_DRIVE_STRENGTH_MAX

enum wm_adc_gain1_level_t

Values:

enumerator WM_ADC_GAIN1_LEVEL_0

enumerator WM_ADC_GAIN1_LEVEL_1

enumerator WM_ADC_GAIN1_LEVEL_2

enumerator WM_ADC_GAIN1_LEVEL_3

enumerator WM_ADC_GAIN1_LEVEL_4

enumerator WM_ADC_GAIN1_LEVEL_5

enum wm_adc_gain2_level_t

Values:

enumerator WM_ADC_GAIN2_LEVEL_0

enumerator WM_ADC_GAIN2_LEVEL_1

enumerator WM_ADC_GAIN2_LEVEL_2

enumerator WM_ADC_GAIN2_LEVEL_3

enum wm_adc_channel_t

Values:

enumerator WM_ADC_CHANNEL_0

enumerator WM_ADC_CHANNEL_1

enumerator WM_ADC_CHANNEL_2

enumerator WM_ADC_CHANNEL_3

enumerator WM_ADC_CHANNEL_0_1_DIFF_INPUT

enumerator WM_ADC_CHANNEL_2_3_DIFF_INPUT

enumerator WM_ADC_CHANNEL_MAX

enum wm_adc_internal_channel_t

Values:

enumerator WM_ADC_CHANNEL_TEMP

enumerator WM_ADC_CHANNEL_VOLT

enumerator WM_ADC_CHANNEL_OFFSET

enum wm_adc_intr_type_t

Values:

enumerator WM_ADC_INTR_TYPE_ADC

enumerator WM_ADC_INTR_TYPE_DMA

enumerator WM_ADC_INTR_TYPE_COMP

enumerator WM_ADC_INTR_TYPE_MAX

enum wm_i2s_mode

i2s select master or slave

Values:

enumerator WM_I2S_MODE_MASTER

enumerator WM_I2S_MODE_SLAVE

enumerator WM_I2S_MODE_MAX

enum wm_i2s_dir

Values:

enumerator WM_I2S_DIR_IN

enumerator WM_I2S_DIR_OUT

enumerator WM_I2S_DIR_INOUT

enumerator WM_I2S_DIR_MAX

enum wm_i2s_std

The standard of I2S to use.

Values:

enumerator WM_I2S_STD_I2S

enumerator WM_I2S_STD_MSB

enumerator WM_I2S_STD_PCMA

enumerator WM_I2S_STD_PCMB

enumerator WM_I2S_STD_MAX

enum wm_i2s_fmt

The format of frame.

警告

For 24 bit sampling, it is necessary to expand 24 bits to 32 bits before sending, and all the high 8 bits are 0. After receiving, it is necessary to remove the high 8 bits and restore them to 24 bits.

Values:

enumerator WM_I2S_FMT_8BIT

enumerator WM_I2S_FMT_16BIT

enumerator WM_I2S_FMT_24BIT

enumerator WM_I2S_FMT_32BIT

enumerator WM_I2S_FMT_MAX

enum wm_i2s_chan_type

The type of channel.

Values:

enumerator WM_I2S_CHAN_TYPE_MONO

enumerator WM_I2S_CHAN_TYPE_STEREO

enumerator WM_I2S_CHAN_TYPE_MAX

enum wm_i2s_pins

Using the I2S interface with GPIO pins.

Values:

enumerator WM_I2S_PIN_MCLK

enumerator WM_I2S_PIN_BCLK

enumerator WM_I2S_PIN_LRCLK

enumerator WM_I2S_PIN_OUT

enumerator WM_I2S_PIN_IN

enumerator WM_I2S_PIN_MAX

enum wm_i2s_xfer_type

The method of data displacement.

Values:

enumerator WM_I2S_XFER_DMA: xfer data with DMA by default

enumerator WM_I2S_XFER_MAX

enum wm_i2s_irq_mask_t

i2s interrupt mask

Values:

enumerator WM_I2S_RXFIFO_UNDERFLOW_IRQ_MASK

enumerator WM_I2S_RXFIFO_OVERFLOW_IRQ_MASK

enumerator WM_I2S_RXFIFO_THRESHOLD_IRQ_MASK

enumerator WM_I2S_RXDONE_IRQ_MASK

enumerator WM_I2S_TXFIFO_UNDERFLOW_IRQ_MASK

enumerator WM_I2S_TXFIFO_OVERFLOW_IRQ_MASK

enumerator WM_I2S_TXFIFO_THRESHOLD_IRQ_MASK

enumerator WM_I2S_TXDONE_IRQ_MASK

enumerator WM_I2S_RIGHT_ZERO_CROSS_IRQ_MASK

enumerator WM_LL_I2S_LEFT_ZERO_CROSS_IRQ_MASK

enum wm_i2s_irq_flag_t

i2s interrupt flag

Values:

enumerator WM_I2S_RXFIFO_UNDERFLOW_FLAG

enumerator WM_I2S_RXFIFO_OVERFLOW_FLAG

enumerator WM_I2S_RXFIFO_THRESHOLD_FLAG

enumerator WM_I2S_RXDONE_FLAG

enumerator WM_I2S_TXFIFO_UNDERFLOW_FLAG

enumerator WM_I2S_TXFIFO_OVERFLOW_FLAG

enumerator WM_I2S_TXFIFO_THRESHOLD_FLAG

enumerator WM_I2S_TXDONE_FLAG

enumerator WM_I2S_RIGHT_ZERO_CROSS_FLAG

enumerator WM_I2S_LEFT_ZERO_CROSS_FLAG

enumerator WM_I2S_RX_OR_TX_FLAG

enumerator WM_I2S_RECEIVE_FLAG

enumerator WM_I2S_TRANSMISSION_FLAG

enum wm_i2s_irq_flag_clear_t

clear i2s interrupt flag

Values:

enumerator WM_I2S_RXFIFO_UNDERFLOW_FLAG_CLEAR

enumerator WM_I2S_RXFIFO_OVERFLOW_FLAG_CLEAR

enumerator WM_I2S_RXDONE_FLAG_CLEAR

enumerator WM_I2S_TXFIFO_UNDERFLOW_FLAG_CLEAR

enumerator WM_I2S_TXFIFO_OVERFLOW_FLAG_CLEAR

enumerator WM_I2S_TXDONE_FLAG_CLEAR

enumerator WM_I2S_RIGHT_ZERO_CROSS_FLAG_CLEAR

enumerator WM_LL_I2S_LEFT_ZERO_CROSS_FLAG_CLEAR

typedef enum wm_dma_ch_e wm_dma_ch_t: W800 DMA channel enum.

typedef enum wm_dma_ch_irq_e wm_dma_ch_irq_t: dma ch interrupt id

typedef enum wm_dma_ch_uart_sel_e wm_dma_ch_uart_sel_t: dma uart dma channel

typedef enum wm_dma_req_sel_e wm_dma_req_sel_t: dma request source

typedef enum wm_dma_int_type_e wm_dma_int_type_t: dma ch interrupt type

typedef enum wm_dma_op_mode_e wm_dma_op_mode_t: dma mode

typedef enum wm_dma_chain_mode_e wm_dma_chain_mode_t: dma chain mode

typedef enum wm_dma_reload_e wm_dma_reload_t: dma auto reload control

typedef enum wm_dma_ch_en_ctrl_e wm_dmach_en_ctrl_t: dma ch interrupt control

typedef enum wm_dma_warp_mode_ctrl_e wm_dma_warp_mode_ctrl_t: dma warp mode control

typedef enum wm_dma_chain_mode_ctrl_e wm_dma_chain_mode_ctrl_t: dma chain mode control

typedef enum wm_dma_addr_mode_e wm_dma_addr_mode_t: dma addr inc mode

typedef enum wm_dma_xfer_uint_e wm_dma_xfer_uint_t: dma data xfer uint

typedef enum wm_dma_burst_uint_e wm_dma_burst_uint_t: dma data burst uint

typedef enum wm_dma_ch_control_e wm_dma_ch_control_t: dma start/stop

typedef enum wm_dma_running_sts_e wm_dma_running_sts_t: dma running status

typedef struct wm_dma_sts_info_s wm_dma_sts_info_t

const wm_io_mux_attr_t g_iomux_attr_table[22]

const wm_gpio_map_t g_gpio_map[48]

WM_PLL_CLOCK

UNIT_MHZ

WM_APB_CLOCK

WM_RCC_I2C_GATE_EN

WM_RCC_UART0_GATE_EN

WM_RCC_UART1_GATE_EN

WM_RCC_UART2_GATE_EN

WM_RCC_UART3_GATE_EN

WM_RCC_UART4_GATE_EN

WM_RCC_UART5_GATE_EN

WM_RCC_LS_SPI_GATE_EN

WM_RCC_DMA_GATE_EN

WM_RCC_RF_CFG_GATE_EN

WM_RCC_TIMER_GATE_EN

WM_RCC_GPIO_GATE_EN

WM_RCC_SD_ADC_GATE_EN

WM_RCC_PWM_GATE_EN

WM_RCC_LCD_GATE_EN

WM_RCC_I2S_GATE_EN

WM_RCC_RSA_GATE_EN

WM_RCC_GPSEC_GATE_EN

WM_RCC_SDIOM_GATE_EN

WM_RCC_QSRAM_GATE_EN

WM_RCC_BT_GATE_EN

WM_RCC_TOUCH_GATE_EN

WM_RCC_CLOCK_ALL

WM_RCC_BBP_RST

WM_RCC_MAC_RST

WM_RCC_SEC_RST

WM_RCC_SDIO_AHB_RST

WM_RCC_DMA_RST

WM_RCC_MEM_MNG_RST

WM_RCC_APB_RST

WM_RCC_BUS1_RST

WM_RCC_BUS2_RST

WM_RCC_I2C_RST

WM_RCC_UART0_RST

WM_RCC_UART1_RST

WM_RCC_UART2_RST

WM_RCC_UART3_RST

WM_RCC_UART4_RST

WM_RCC_UART5_RST

WM_RCC_SPIM_RST

WM_RCC_SPIS_RST

WM_RCC_RF_CFG_RST

WM_RCC_GPIO_RST

WM_RCC_TIMER_RST

WM_RCC_SAR_ADC_RST

WM_RCC_PWM_RST

WM_RCC_LCD_RST

WM_RCC_I2S_RST

WM_RCC_RSA_RST

WM_RCC_GPSEC_RST

WM_RCC_SDIOM_RST

WM_RCC_QSPI_RAM_RST

WM_RCC_BT_RST

WM_RCC_FLASH_RST

WM_RCC_TOUCH_RST

WM_DMA_CH7_XFER_DONE: dma channel 7 transfer done

WM_DMA_CH7_XFER_DONE_POS: dma channel 7 transfer done pos

WM_DMA_CH7_BURST_DONE: dma channel 7 burst done

WM_DMA_CH7_BURST_DONE_POS: dma channel 7 burst done pos

WM_DMA_CH6_XFER_DONE: dma channel 6 transfer done

WM_DMA_CH6_XFER_DONE_POS: dma channel 6 transfer done pos

WM_DMA_CH6_BURST_DONE: dma channel 6 burst done

WM_DMA_CH6_BURST_DONE_POS: dma channel 6 burst done pos

WM_DMA_CH5_XFER_DONE: dma channel 5 transfer done

WM_DMA_CH5_XFER_DONE_POS: dma channel 5 transfer done pos

WM_DMA_CH5_BURST_DONE: dma channel 5 burst done

WM_DMA_CH5_BURST_DONE_POS: dma channel 5 burst done pos

WM_DMA_CH4_XFER_DONE: dma channel 4 transfer done

WM_DMA_CH4_XFER_DONE_POS: dma channel 4 transfer done pos

WM_DMA_CH4_BURST_DONE: dma channel 4 burst done

WM_DMA_CH4_BURST_DONE_POS: dma channel 4 burst done pos

WM_DMA_CH3_XFER_DONE: dma channel 3 transfer done

WM_DMA_CH3_XFER_DONE_POS: dma channel 3 transfer done pos

WM_DMA_CH3_BURST_DONE: dma channel 3 burst done

WM_DMA_CH3_BURST_DONE_POS: dma channel 3 burst done pos

WM_DMA_CH2_XFER_DONE: dma channel 2 transfer done

WM_DMA_CH2_XFER_DONE_POS: dma channel 2 transfer done pos

WM_DMA_CH2_BURST_DONE: dma channel 2 burst done

WM_DMA_CH2_BURST_DONE_POS: dma channel 2 burst done pos

WM_DMA_CH1_XFER_DONE: dma channel 1 transfer done

WM_DMA_CH1_XFER_DONE_POS: dma channel 1 transfer done pos

WM_DMA_CH1_BURST_DONE: dma channel 1 burst done

WM_DMA_CH1_BURST_DONE_POS: dma channel 1 burst done pos

WM_DMA_CH0_XFER_DONE: dma channel 0 transfer done

WM_DMA_CH0_XFER_DONE_POS: dma channel 0 transfer done pos

WM_DMA_CH0_BURST_DONE: dma channel 0 burst done

WM_DMA_CH0_BURST_DONE_POS: dma channel 0 burst done pos

WM_DMA_CH07_INT_MAP: dma all ch interrupt mask

WM_DMA_LIST_VLD: dma desc list valid bit

WM_SDH_DATA_BUF_BYTES

WM_SDH_BLOCK_SIZE

WM_UART_HW_FIFO_NUM

WM_GPIO_MAX_NUM_BY_ALL_SOC

WM_GPIO_PIN_VALID(pin_no)

WM_IOMUX_ATTR_NUM

WM_GPIO_DIR_DEFAULT

WM_PWM_PERIOD_DEFAULT: default output pwm period cycle set to 200 times pwm clocks

WM_PWM_DUTY_CYCLE_DEFAULT: default output pwm duty cycle set to 40 times pwm clocks

WM_PWM_CLKDIV_DEFAULT: default output pwm frequency set to 10kHz for 40MHz main clock and 200 pwm period cycle

WM_PWM_MAX_PERIOD: max period value can be set PWM module register, final value will incremented by 1

WM_PWM_MIN_PERIOD: min period value can be set PWM module registerk0k, final value will be incremented by 1

WM_PWM_MAX_CLKDIV: max clock divider value can be set PWM module register, final value will incremented by 1

WM_PWM_MIN_CLKDIV: min clock divider value can be set PWM module register, final value will incremented by 1

WM_PWM_MAX_DT_CLKDIV: the max clock divider for deadtime

WM_TOUCH_THRESHOLD_MAX

WM_TOUCH_NUM_MAX

WM_ADC_RESULT_MASK

WM_ADC_MAX_CHANNEL_COUNT

WM_I2S_MCLK_DIV_MIN: min divider value support for I2S mclk

WM_I2S_MCLK_DIV_MAX

WM_I2S_BCLK_DIV_MIN

WM_I2S_BCLK_DIV_MAX

I2S_INT_MASK: I2S all interrupt mask bitmap

I2S_INT_GET_SRC: get I2S all interrupt src bitmap

I2S_INT_CLS_SRC: clear I2S all interrupt src bitmap

struct wm_dma_sts_info_s

struct wm_gpio_map_t

struct wm_io_mux_attr_t